VHDL - Programming the Field Programmable Gate Array (FPGA)
First, we have to construct a truth table for a 2-to-4 decoder. We will utilize the truth table to analyze the required circuit. The decoder, as it is indicated in table1 below, has three input signals (enable input signal with two selector switches) and four output ports. The enable signal is used to control the outputs by turning the decoder operation either ON or OFF. The combination of the input signals, S1 and S2, results a unique binary output.
When the enable switch is set to zero, regardless of the position of switch one or two, all the outputs will be zero. However, when the enable switch is set to one, the outputs will depend upon the position of both switch one and two. In this situation, the two binary inputs, S1 and S2, are decoded into one of the four outputs. For instance, when both S1and S2 are set to zero, L3 will be logic “high.” Therefore, only one output will be binary “one” at a given time. In this pattern, one of the output will represent the corresponding min-term for the input signals.
Next, create a test bench containing all input possibilities to validate the proper functionality of the VHDL code as well as the complete circuit design. Here, we will modify the default test bench code as it has clock signals; however, this design does not require the clock input. Therefore, remove all the codes that contains clock signal.
2 to 4 Decoder Testbench code
Next, check the testbench code for syntax errors, and adjust the simulation run time to 100ns to allow the testbench code goes through all the possible combinations of the inputs. Then, run the simulation to obtain a waveform similar to the figure shown below.
2 to 4 Decoder Waveform
User Constraint File (UCF) for - Basys 2 FPGA Board
Create the implementation UCF file (.ucf) as shown bellow. This file contains the signal definitions and physical mapping of the pins on the Basys-2 FPGA board.
NET "led" LOC = M5;
NET "led" LOC = M11;
NET "led" LOC = P7;
NET "led" LOC = P6;
NET "enable" LOC = K3;
NET "sw" LOC = P11;
NET "sw" LOC = L3;
Finally, generate a programming file (.bit), Connect the FPGA board to the computer and program the FPGA board using the ADEPT software.