Hardware description languages (HDLs) allow designers of digitals systems to enter the functionality of the design using text coding. Today, VHDL and Verilog are the two most commonly used HDLs tools. In this tutorial, we will be covering the Verilog Hardware Description Language.
Verilog is a hardware description language (HDL) which is a text format to describe electronic circuits and systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level (RTL) of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.
In Verilog, the behavioral modeling is used to describe the design at a high-level of abstraction using library parts like gates, flip-flops, registers, and memories. The structural modeling is used to describe the design as interconnection of modules.
Data Types In Verilog, every signal, constant, variable, and function must be assigned a data type. Some data types are synthesizable, while others are only for modeling purpose only. The following are the most commonly used data types. 1. Value Set Data Type Verilog consists of four basic value set data types that a signal can take on. Almost all Verilog data types store all these values:
logic zero, or false condition
logic one, or true condition
unknown logic value
high impedance state
2. Wire Data Type A wire is the most widely used "net" data type that represents a physical wire in a circuit and is used to connect gates or components. The value of a wire can be read, but not assigned to, in a function or block. There are other net data types like wor (wired-OR), wand(wired-AND'd), ... and many more. In this tutorial, we will use only the wire net data type.
3. Variable Data Types In Verilog, there are five variable data types: reg, integer, real, time, and realtime. These data types are used as a model storage. - reg: models a logic storage variable. - integer: models a 32-bit variable for whole numbers. - real: models a 64-bit variable for floating numbers. - time: 64-bit variable for simulation purpose. - realtime: similar to time with readability.
4. Vector Data Type A vector is a one-dimensional array of the net data and the reg data types. Syntax: <dataType> [<MSB>:<LSB>] vectorName Example: wire [3:0] product; //4-bit vector named "product" of wire data type
5. Array Array is a multidimensional set of elements or vectors of vectors with the same dimensions. Array is declared in a way that the element type and dimension are defined first and the array name and dimension will be decaled next. Syntax: <element_type> [<MSB>:<LSB] array_name [<array_start: <array_end>]; Example: reg [3:0] Mem [0:255]; // An array of 256, 4-bit vectors of type register.
6. Parameter A parameter or constant defines a quantity that will be used reputedly throughout the module. This allows customization of a module during instantiation. Syntax: parameter <type> parameter_name = <value>; Example: parameter open = 1;
1. Assignment Operator Verilog uses the equal sign (=) to create a module assignment. Example: A = 2'b01; // A is assigned a value of binary 01 and it is a 2-bit vector.
2. Continuous Assignment Continuous assignment uses the keyword "assign" for signal assignment. Before assigning a value, the net must be declared. Example: wire A; // A is declared as an internal net (wire) assign A = 2'b01; // A is assigned a value of 1
3. Arithmetic Operators Arithmetic operators perform numerical operations. Example A + B; // addition A - B; // subtraction A * B; // multiplication A / B; // division A % B; // modulus of A/B A ** B // A to the power of B
4. Bitwise Operators Bitwise operators perform a single bit logical functions on individual bits. Example: ~X; // bitwise NOT A & B; // bitwise AND A | B; // bitwise OR A ^ B; // bitwise XOR A ~^ B; // bitwise XNOR << ; // bitwise shift left >> ; // bitwise shift right
5. Boolean Operators A Boolean logic operator returns a value of 1 (TRUE or 0 (FLASE). Example: !A ; // not A (logical NOT) A && B; // A AND B (logical AND) A || B ; // A OR B (logical OR)
6. Relational Operators Relational operators compare two operands and return a single bit 1or 0. < (less than) <= (less than or equal to) > (greater than) >= (greater than or equal to) == (equal to) != (not equal to) Example: if (A == B) F= 1; // TRUE if A is equal to B and assign the value of 1 to F else F=0; // FALSE if A is not equal to B and assign the value of 0 to F