Verilog Construction - Behavioral ModelingVerilog Module A Verilog module, similar to class in C++, is encapsulated inside the keyword "module" and "endmodule". It includes the inputs and outputs of the system and the description of the design behavior. A module may also declare additional variables.
The body of a module consists of: ■ initial constructs, which can initialize reg variables ■ continuous assignments, which define only combinational logic ■ "always" constructs, which can define either sequential or combinational logic ■ instances of other modules, which are used to implement the module being defined Example1: Pre-2001 Verilog style The example below shows the pre-2001 Verilog style that uses the following syntax: module <moduleName> (port_list); // port definitions // behavior description endmodule
Example2: Post-2001 Verilog style
Example 2 shows the post-2001 Verilog style the uses the following constructs; (in this tutorial we will be using the post-2001 Verilog style.) module <moduleName> (<port_list and port_definitions>); // behavior description endmodule
Verilog Module Continuous AssignmentsIn Verilog, a continuous assignment is used to assign a value onto a wire. When the model is described using continuous assignments, each lines of code represent the behavior of the system. Therefore, each lines of code are executed concurrently. The order of the assignments does not matter. Any change in any of the right-hand-side (inputs) will immediately change a left-hand-side (output).
A continuous assignment, which is indicated with the keyword "assign", acts like a combinational logic function: the output is continuously assigned the value, and a change in the input values is reflected immediately in the output value.
Example4: Truth Table Implementation with Continuous Assignment.
Example 4 shows modeling combinational logics using continuous assignments and direct interpretation of a truth table. This method is not cost effective as it uses more logic devices than example 3. Therefore, the truth table should be simplified using a K-map and the simplified logical expression should be used. However, this example is only demonstrating the capabilities of Verilog Hardware Description Language.
Example5: Half-adder with Continuous Assignment.
Example 5 shows modeling a half-adder using continuous assignments. Assign statements are one way to write a Verilog code that generates combinational logic. However, for more complex structures, assign statements may be awkward or tedious to use.
Half-adder Vivado schematic
Blocking and non-blocking assignments
Blocking assignments are order sensitive, but non-blocking assignments are order independent. Which means, blocking assignments are executed sequentially in the order that they appeared in a procedural block. However, non-blocking assignments are executed concurrently. The blocking assignment operator is an equal sign ("="). A blocking assignment must evaluate the RHS arguments and complete the assignment without interruption from any other Verilog statement. It is called "blocking" because it blocks other assignments until the current assignment execution has completed. The nonblocking assignment operator is a less-than-or-equal-to operator ("<="). A nonblocking assignment evaluates the RHS expression of a nonblocking statement at the beginning of a clock and schedules the LHS update to take place at the end of the clock period. non-blocking assignments are executed in parallel independent of their order. 
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