Verilog Construction - Behavioral ModelingVerilog Module A Verilog module is encapsulated inside the keyword "module" and "endmodule". It includes the inputs and outputs of the system and the description of the design behavior.
Example1: Pre-2001 Verilog style The example below shows the pre-2001 Verilog style that uses the following syntax: module <moduleName> (port_list); // port definitions // behavior description endmodule Example2: Post-2001 Verilog style
Example 2 shows the post-2001 Verilog style the uses the following constructs; (in this tutorial we will be using the post-2001 Verilog style.) module <moduleName> (<port_list and port_definitions>); // behavior description endmodule
Verilog Module Continuous AssignmentsIn Verilog, a continuous assignment is used to assign a value onto a wire. When the model is described using continuous assignments, each lines of code represent the behavior of the system. Therefore, each lines of code are executed concurrently. The order of the assignments does not matter. Any change in any of the right-hand-side (inputs) will immediately change a left-hand-side (output).
Example4: Truth Table Implementation with Continuous Assignment.
Example 4 shows modeling combinational logics using continuous assignments and direct interpretation of a truth table. This method is not cost effective as it uses more logic devices than example 3. Therefore, the truth table should be simplified using a K-map and the simplified logical expression should be used. However, this example is only demonstrating the capabilities of Verilog Hardware Description Language.
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