Verilog Construction - Behavioral Modeling

Verilog Module ​

A Verilog ​module, similar to class in C++, is encapsulated inside the keyword "module" and "endmodule". It includes the inputs and outputs of the system and the description of the design behavior.  A module may also declare additional variables.
The body of a module consists of:
■ initial constructs, which can initialize reg variables
■ continuous assignments, which define only combinational logic
■ "always" constructs, which can define either sequential or combinational logic
■ instances of other modules, which are used to implement the module being defined
​
Example1: Pre-2001 Verilog style
The example below shows the pre-2001 Verilog style that uses the following syntax:
module <moduleName> (port_list); 
     // port definitions
     // behavior description
endmodule

---

Line #1 shows single line comment
Line #2 shows keyword "module", module name, and a port            name & direction. 
Line #3 shows remaining port name definitions.

Line #5 shows internal signal declaration

Line #8 thru 10 show the behavioral description 

Line # 12 shows the keyword "endmodule"

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Example2: Post-2001 Verilog style
Example 2 shows the post-2001 Verilog style the uses the following constructs; (in this tutorial we will be using the post-2001 Verilog style.)
​module <moduleName> (<port_list and port_definitions>); 
     // behavior description
endmodule

Post-2001 Verilog allows the port name, direction, and type to be declared together.  
​
- Each port needs to have a user-defined name.
- ​The port directions are declared to be one of the three types: input, output, or inout.
- A port can take on any of the data types, but only wires, registers, and integers are synthesizable.

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Verilog Module ​Continuous Assignments

In Verilog, a continuous assignment is used to assign a value onto a wire. When the model is described using continuous assignments, each lines of code represent the behavior of the system. Therefore, each lines of code are executed concurrently. The order of the assignments does not matter. Any change in any of the right-hand-side (inputs) will immediately change a left-hand-side (output).

A continuous assignment, which is indicated with the keyword "assign", acts like a combinational logic function: the output is continuously assigned the value, and a change in the input values is reflected immediately in the output value. 

Example3: Continuous Assignments.
​Example 3 shows modeling combinational logics using continuous assignments.

​Let's use an arbitrary logical expression:
F = (A.B) + (A.C) + (B.C)
Here, three AND gates will be connected to an OR gate
therefore, we need three internal wires. Let's name them
AB, AC, and BC and these nets will be of "wire" data type.

Line #1 thru 4 show block comments

Line #5 shows the post-2001 Verilog style of port name, direction, and type declaration.

Line #9, internal signal definition of type wire

Line #12 thru 16 describe the behavior the logical expression F = (A.B) + (A.C) + (B.C)

 

Example4: Truth Table Implementation with Continuous Assignment.
​Example 4 shows modeling combinational logics using continuous assignments and direct interpretation of a truth table. This method is not cost effective as it uses more logic devices than example 3. Therefore, the truth table should be simplified using a K-map and the simplified logical expression should be used. However, this example is only demonstrating the capabilities of Verilog Hardware Description Language.

​Line #1 thru 16 uses the block comment to describe the problem statement and the truth table.

We can use only expressions resulting a logic "1" output to create an SOP expression. Therefore, we can use line #10, 12, 13, and 14 for the SOP equation.

​Line #18 and 19 show the port name, direction, and type declaration.

Line #22 implements the behavior of the module using continuous assignment and logical operators.
​

Example5: Half-adder with Continuous Assignment.
​Example 5 shows modeling a half-adder using continuous assignments. Assign statements are one way to write a Verilog code that generates combinational logic. However, for more complex structures, assign statements may be awkward or tedious to use. 

​Line #4 two 1-bit inputs
Line #5 two 1-bit outputs
Line #7 continuous assignment, Sum is A XOR B
Line #8 continuous assignment, Carry is A AND B
​

Half-adder Vivado schematic

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