VHDL - Programming the Field Programmable Gate Array (FPGA)
2 to 4 Binary Decoder VHDL Design
In this tutorial, we will design and implement a 2-to-4 Decoder by utilizing the Xilinx ISE CAD tool and Basys 2 FPGA board. The implementation will be on a Field Programmable Gate Array (FPGA) board and we will be using VHDL programming language.
VHDL V - VHSIC: Very High Speed Integrated Circuit H - Hardware D- Description L - Language
First, we have to construct a truth table for a 2-to-4 decoder. We will utilize the truth table to analyze the required circuit. The decoder, as it is indicated in table1 below, has three input signals (enable input signal with two selector switches) and four output ports. The enable signal is used to control the outputs by turning the decoder operation either ON or OFF. The combination of the input signals, S1 and S2, results a unique binary output. When the enable switch is set to zero, regardless of the position of switch one or two, all the outputs will be zero. However, when the enable switch is set to one, the outputs will depend upon the position of both switch one and two. In this situation, the two binary inputs, S1 and S2, are decoded into one of the four outputs. For instance, when both S1and S2 are set to zero, L3 will be logic “high.” Therefore, only one output will be binary “one” at a given time. In this pattern, one of the output will represent the corresponding min-term for the input signals.
2 to 4 Decoder VHDL Code
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dec2to4 is Port ( enable : in STD_LOGIC; sw : in STD_LOGIC_VECTOR (1 downto 0); led : out STD_LOGIC_VECTOR (3 downto 0)) end dec2to4; architecture Behavioral of dec2to4 is begin led <= "0000" when enable = '0' else "0001" when sw = "00" else "0010" when sw = "01" else "0100" when sw = "10" else "1000"; end Behavioral;
Truth table for 2 to 4 Decoder
Next, create a test bench containing all input possibilities to validate the proper functionality of the VHDL code as well as the complete circuit design. Here, we will modify the default test bench code as it has clock signals; however, this design does not require the clock input. Therefore, remove all the codes that contains clock signal. 2 to 4 Decoder Testbench code
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY dec2to4_test IS END dec2to4_test; ARCHITECTURE behavior OF dec2to4_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dec2to4 PORT( enable : IN std_logic; sw : IN std_logic_vector(1 downto 0); led : OUT std_logic_vector(3 downto 0)); END COMPONENT; --Inputs signal test_seq : std_logic_vector(2 downto 0); --Outputs signal led : std_logic_vector(3 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: dec2to4 PORT MAP ( enable => test_seq(2), sw => test_seq (1 downto 0), led => led ); -- Stimulus process stim_proc: process begin -- insert stimulus here test_seq<="000"; wait for 10ns; test_seq<="001"; wait for 10ns; test_seq<="010"; wait for 10ns; test_seq<="011"; wait for 10ns; test_seq<="100"; wait for 10ns; test_seq<="101"; wait for 10ns; test_seq<="110"; wait for 10ns; test_seq<="111"; wait; end process; END;
Then, check the testbench code for syntax errors, and adjust the simulation run time to 100ns to allow the testbench code goes through all the possible combinations of the inputs. Next, run the simulation to obtain a waveform similar to the figure shown below.
2 to 4 Decoder Waveform
User Constraint File (UCF) for - Basys 2 FPGA Board
Create the implementation UCF file (.ucf) as shown bellow. This file contains the signal definitions and physical mapping of the pins on the Basys-2 FPGA board. NET "led" LOC = M5; NET "led" LOC = M11; NET "led" LOC = P7; NET "led" LOC = P6; NET "enable" LOC = K3; NET "sw" LOC = P11; NET "sw" LOC = L3;
Finally, generate a programming file (.bit), Connect the FPGA board to the computer and program the FPGA board using the ADEPT software.