Verilog HDL Examples using Xilinx ISE Project Navigator

Example 1.
​4-Bit Binary Counter
The following example demonstrates how we can model a 4-bit binary counter in Verilog. We will use the Verilog "numerical operators" on the "reg" data type such that the counter behavior can be expressed as Counter = Counter + 1 to increment the counting procedure. 

- Count is a 4-bit Output with "reg" data type.

- Clock and Reset signals are listed in the sensitivity list.
- Non-blocking procedural assignment handles the reset condition. 
- ​if-else statement is used to handle both the reset and increment behaviors.

4-Bit Binary Counter Waveform. Counting from 0000 to 1111.

Example 2.
​4-Bit Counter with Enable
Enable circuit is used to protect the counter from running continuously. When enable is triggered, the counter will increment or decrement on the next positive edge of the clock cycle. When enable is removed, the counter will hold the previous value until the next enable signal is asserted. Example 2 demonstrates how we can model a 4-bit binary counter with enable function. 

- Enable is added to the port declaration. 
- If enable is asserted, the counter will increment on the rising edge of the clock. 
- Enable is synchronous, meaning that it is only evaluated on the rising edge of the clock and it is modeled as a nested if-else statement within the main if-else statement.
​

4-Bit Counter with Enable. When enable is removed, the counter will hold the last value.

Example 3.
​4-Bit Up/Down Counter with Enable and Up/notUp select switch
In  this example, we will see how to model an up-down  counter with an enable function and up/down selector that will set the counter to count either incrementing or decrementing. This example also shows a "timescale" directive that will define the timescale of the delay unit and its smallest precision. A timescale 1ns/1ps  declares the unit of time is 1 ns with a precision of 1ps. 

Line #1 shows 'timescale directive 1ns/1ps which declares the unit of time is 1 ns with a precision of 1ps.
Line #3 has additional "UP" input to select up/down counting.
 - When UP is asserted the counter will count up. 
 - When UP deserted the counter will count down.
​ 

4-Bit Up/Down Counter with Enable and Up/notUp select switch.

​Example 4.
​4-Bit Counter with Enable and Load
​In this example, we will see how to model a counter with an enable function and a load input that will set the counter to a specified value. A counter with a load will set the counter to a specified value from the input port "start_number". The input "start_number" will be loaded to the counter when the "load" signal is asserted and when the clock is its rising edge.
​

Line #1 shows 'timescale directive 1ns/1ps
 - Load and start_number inputs added
 - Load signal is modeled in a nested if-else statement to assert the input "start_number" that will be available to the counter at the next rising edge of the clock.
​
 - When Load signal is asserted, the counter will be updated with new value.
 

4-Bit Counter with Enable and Load.

---

Verilog HDL Examples using Xilinx/AMD Vivado 

​Example 5.
​ALU (Arithmetic and Logic Unit)
​In this example, we will see how to design a Verilog behavioral model of ALU. The module is synthesized using basic libraries containing arithmetic and logical operations. 

ALU Verilog HDL code

ALU testbench

ALU waveform

---

Back>> Verilog Construction

PAGE TAGS AutoCAD CAD CATIA Digital Logic Matlab VHDL Links Programming VHDL Verilog Xilinx AMD

Back>> Verilog Construction

---